1. Field of the Invention
The present invention relates to a sampling rate converter of a simple circuit arrangement, and more particularly to a sampling rate converter suitable for use in a digital audio device.
2. Description of the Prior Art
There is known a sampling rate converter employing a digital filter, as disclosed in Japanese Laid-Open Patent Publication No. 57-115015, for example.
FIG. 1 of the accompanying drawings shows a conventional sampling rate converter. The sampling rate converter shown in FIG. 1 includes a time difference measuring circuit 1 for measuring the time difference between an input sampling rate and an output sampling rate (i.e., the phase difference between sampling clock pulses for input data and sampling clock pulses for output data). The time difference information from the time difference measuring circuit 1 is supplied to a time difference to coefficient converter 2, and converted thereby into a filter coefficient, which is then supplied to a sampling filter (digital filter) 3. As shown in detail in FIG. 2, the time difference measuring circuit 1 comprises a phase-locked loop 4 and a counter 5. The time difference measuring circuit 1 starts counting clock pulses in response to a signal indicative of the input sampling rate and stops counting clock pulses in response to a signal indicative of the output sampling rate. When the time difference measuring circuit 1 stops counting clock pulses, it supplies its count represented by parallel data to the time difference to coefficient converter 2. The phase-locked loop 4 supplies the counter 5 with a frequency signal, as clock pulses, which is held in phase with the input sampling rate signal.
To increase the sampling rate with the sampling filter 3 in FIG. 1, sampled values of zero (or linearly interpolated values) are inserted between the original sampled values, providing a new sampled sequence, which is then processed by the sampling filter 3 at a higher sampling rate. In this manner, the output sampling rate can be increased. If the sampling rate is to be increased in a number of steps, then the above process has to be repeated a plurality of times. Therefore, the entire processing operation is complex, and the required circuit arrangement is also complex.